A. Venkatareddy

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Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly leakage power and stability. A new seven transistor SRAM (7T) is proposed in this paper which eliminates the stability issues, reliable write and has a reduced cell area. Leakage current in proposed 7T SRAM cell without Super cut-off word lines is almost same as in 6T SRAM(More)
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