A. Salem

Learn More
Most recent combinational equivalence checking techniques are based on exploiting circuit similarity. In this paper, we focus on circuits with no internal equivalent nodes or after internal equivalent nodes have been identified and merged. We present a new technique integrating Boolean Satisfiability and Binary Decision Diagrams. The proposed approach is(More)
In this paper, a Branch-and-Bound (B&B) algorithm is presented to solve the problem of minimizing the maximum completion time C max on unrelated parallel machines with machine eligibility restrictions when job preemption is not allowed. A customized lower bound, a search and a branching strategy are developed for the B&B. A machine eligibility factor is(More)
  • 1