A. Ranade

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In this report we study the oating random walk method for Capacitance Estimation in VLSI circuits. The aspects studied are the time complexity of the algorithm, error reduction and ways to speed the algorithm. For algorithms such as these, most of the analysis done in the literature is based only on experimental results. We take a theoretical approach(More)
To those who probably will understand the least, but matter the most. iii ACKNOWLEDGEMENTS First and foremost, I thank my advisor, Vijay Vazirani, for his constant support, advice and help throughout these five years. I hope I have imbibed an of the infinite energy with which he does research. Thanks Vijay for everything! I thank Prasad Tetali for patiently(More)
A graph is planar if it can be drawn in the plane without edges crossing. More formally, a graph is planar if it has an embedding in the plane, in which each vertex is mapped to a distinct point P (v), and edge (u, v) to simple curves connecting P (u), P (v), such that curves intersect only at their endpoints. graph which each partition having 3 vertices.(More)
My current research is the design of efficient and practical algorithms for fundamental problems in Machine Learning and Optimization. More specifically, I am interested in decision making under uncertainty, statistical learning theory, combinatorial optimization, and convex optimization techniques such as linear and semidefinite programming.
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