A. Montree

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  • A. Montree
  • 2007 International Symposium on VLSI Technology…
  • 2007
In this paper the voltage scaling of embedded non-volatile memories was discussed. Floating gate cells with high-K IPD and nitride trapping cells with high-K tunnel and blocking layers offer significant reduction of the program/erase efficiency. A major voltage reduction could be achieved by using phase change memory technology that is a serious contender(More)
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