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Scaling of CMOS technologies beyond the 90 nm node requires the reduction of the gate Dielectric thickness down to an Equivalent Oxide Thickness (EOT) of ˜ 1 nm which will either Be realized with SiON or high-k gate dielectrics. Both scenarios, the further scaling of SiON gate Dielectrics or the introduction of high-k dielectrics, bring various(More)
The application of fast measurement techniques for the reliability assessment of sub-100 nm CMOS technologies was recently proposed in the literature. To realize fast wafer level current measurements, ranging from nA to mA, a measurement setup was developed consisting of an analog input/output PCI card and (log-lin) current-voltage converters. With this(More)
To minimize charge relaxation during Bias Temperature Instability (BTI) tests, fast current sensing has become the mainstream methodology in recent years and fast source measurement units are now available commercially. In these instruments, the measurement delay and sampling time have to been significant reduced in order to meet the more stringent(More)