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In this paper, a layout scheme for accurate common-centroid rectangular unit-capacitor arrays is presented with detailed explanation of the rules used to improve matching. This layout technique is combined with a common-centroid arbitrary-value capacitor placement algorithm to form an automatic capacitor array generation tool. Finally, design and(More)
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers(More)
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