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HELIX: automatic parallelization of irregular programs for chip multiprocessing
We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. We show that the inter-thread communication costs
Voltage Noise in Production Processors
TLDR
Researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor and characterize the implications of resilient architecture design for voltage variation in future systems.
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
TLDR
It is shown that a voltage-noise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
HELIX-UP: Relaxing program semantics to unleash parallelization
TLDR
This work has developed a parallelizing compiler and runtime that substantially improve scalability by allowing parallelized code to briefly sidestep strict adherence to language semantics at run time.
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
TLDR
A lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution, shows an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.
IR
3.3 Lateral and rotational supports shall be provided at points of bearing per AF&PA NDS, Section 7.3.5 and shall be located no more than 1 foot from bearing point at supports using joist hangers.
A parallel dynamic compiler for CIL bytecode
TLDR
This work proposes an approach that leverages on CMP features to expose a novel pipeline synchronization model for the internal threads of the dynamic compiler, ILDJIT, and is able to achieve significant speedups with respect to the baseline, when the underlying hardware exposes at least two cores.
Performance implications of transient loop-carried data dependences in automatically parallelized loops
TLDR
This paper confirms the existence of significant extra thread-level parallelism within loops parallelized by the HELIX compiler and develops three approaches to take advantage of the transient nature of these data dependences through speculation, via transactional memory support, and coupling the state-of-the-art data dependence analysis with fine-grained speculation.
Metronome: Operating system level performance management via self-adaptive computing
TLDR
The Metronome framework is presented, a framework to enhance commodity operating systems with self-adaptive capabilities and features two distinct components: Heart Rate Monitor (HRM) and Performance - Aware Fair Scheduler (PAFS).
Eliminating voltage emergencies via software-guided code transformations
TLDR
The proposed technique reassembles a traditional reliability problem as a runtime performance optimization problem, thus allowing us to design processors for typical case operation by building intelligent algorithms that can prevent recurring violations.
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