• Publications
  • Influence
"It's a small world after all": NoC performance optimization via long-range link insertion
TLDR
In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Expand
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
TLDR
We enumerate several related research problems in the design of NoCs. Expand
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Key research problems in NoC design: a holistic perspective
TLDR
We provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Expand
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Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
TLDR
Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known a priori. Expand
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Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
TLDR
This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI Simulation results show about 40% savings for a real video application. Expand
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System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
TLDR
In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. Expand
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An Analytical Approach for Network-on-Chip Performance Analysis
TLDR
We present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. Expand
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On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches
TLDR
We compare and contrast the network-on-chip (NoC) with point-to-point (P2P) and bus-based communication architectures in terms of area, performance, and energy consumption. Expand
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Virtual Channels Planning for Networks-on-Chip
TLDR
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. Expand
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Quick formal modeling of communication fabrics to enable verification
TLDR
We identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. Expand
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