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The ever-shorter time-to-market calls for efficient robust IC design algorithms. Robust circuits satisfy all design requirements across a range of operating conditions and manufacturing process variations. In the paper we propose an automated robust IC design and optimization process derived from the design algorithms utilized manually by experienced analog(More)
Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of(More)
Automating the robust IC design process is becoming more and more important due to its complexity and decreasing time to market. In order for the circuit to be robust it must satisfy all design requirements across a range of operating conditions and manufacturing process variations. Part of the design process, which is performed by experienced analog IC(More)
This paper presents a new optimization algorithm for automatic sizing of integrated circuits (IC) in SPICE. We refer to the new method as DESA. It is a hybrid between two very popular oprimization methods. The first one is differential evolution (DE) which is a robust population based optimization method and has received a lot of attention in the recent(More)
An extension of the global convergence framework for unconstrained derivative free optimization methods is presented. The extension makes it possible for the framework to include optimization methods with varying cardinality of the ordered direction set. Grid-based search methods are shown to be a special case of the more general extended global convergence(More)
Though rather awkward and limited in its usage, SPICE has been used by several authors solving their various optimisation problems. In this paper we propose how some generic optimisation algorithms can be integrated into SPICE. The implemented program has proven to be an extremely efficient optimisation tool for an experienced circuit designer. It is free(More)