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The ever-shorter time-to-market calls for efficient robust IC design algorithms. Robust circuits satisfy all design requirements across a range of operating conditions and manufacturing process variations. In the paper we propose an automated robust IC design and optimization process derived from the design algorithms utilized manually by experienced analog(More)
—The performance requirements and deadlines in analog IC design are becoming more and more difficult to satisfy. Robust design produces circuits that full-fill the design requirements in several different operating environments and under the influence of manufacturing process variations. Generally designers use computers only for evaluating the circuit. A(More)
Automating the robust IC design process is becoming more and more important due to its complexity and decreasing time to market. In order for the circuit to be robust it must satisfy all design requirements across a range of operating conditions and manufacturing process variations. Part of the design process, which is performed by experienced analog IC(More)
Circuit sizing (i.e., determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma; namely, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of(More)
Differential evolution is a simple algorithm for global optimization. Basically it consists of three operations: mutation, crossover and selection. Despite many research papers dealing with the first two, hardly any attention has been paid to the third one nor is there a place for this operation in the algorithm basic naming scheme. In the paper we show(More)
One of the basic algorithms employed in IC design automation is parametric optimization. It is used when a minimum of a so-called cost function is sought. There exist many optimization algorithms. One of the most successful ones is the Box simplex algorithm. The main drawback of this algorithm that was observed in practice is its slow progress in the last(More)
— This paper presents a new hybrid algorithm for global optimization of integrated circuits. The algorithm exploits the efficient search mechanism of differential evolution and good global search capabilities of simulated annealing, while avoiding their weaknesses. It is easy to implement and has only a few parameters. The performance of the algorithm is(More)
The idea of asynchronous parallel optimization oc-cured during the efforts to develop efficient parallel optimization algorithms. Since asynchronous parallel algorithms are more difficult to analyse than their synchronous counterparts, the development of such an algorithm benefits greatly from practical experience. The only way to assess the practical value(More)
This paper presents a new optimization algorithm for automatic sizing of integrated circuits (IC) in SPICE. We refer to the new method as DESA. It is a hybrid between two very popular oprimization methods. The first one is differential evolution (DE) which is a robust population based optimization method and has received a lot of attention in the recent(More)