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Top-Down Design of High-Performance Sigma-Delta Modulators
1. Introduction. 2. Oversampling Sigma-Delta A/D Converters: Basic Concepts and State of the Art. 3. Modeling of Error Mechanisms in Sigma-Delta Modulators. 4. Behavioral Simulation of Sigma-DeltaExpand
ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologiesExpand
Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks
A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net inputExpand
ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy
TLDR
This paper aims to demonstrate the efforts towards in-situ applicability of EMMARM, which aims to provide real-time information about concrete mechanical properties such as E-modulus and compressive strength. Expand
On the design of voltage-controlled sinusoidal oscillators using OTAs
A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTAs) and capacitors is discussed. Two classical oscillator models,Expand
ACE16k: A Programmable Focal Plane Vision Processor with 128 x 128 Resolution
This paper presents a new genera- tion 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabri- cation in a 0.35µmExpand
Nonlinear switched capacitor 'neural' networks for optimization problems
A systematic approach is presented for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques. The method is based on formulating aExpand
Integrated chaos generators
This paper surveys the different design issues, from mathematical model to silicon, involved in the design of analog CMOS integrated circuits for the generation of chaotic behavior.
A 0.8-/spl mu/m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
TLDR
A CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images, based on the cellular neural/nonlinear network universal machine, which features 2-/spl mu/s operation speed and around 7-b accuracy in the analog processing operations. Expand
A VLSI-oriented continuous-time CNN model
TLDR
An analysis of the stability and convergence properties of the Full Signal Range CNN model are demonstrated to be similar to those of the Chua-Yang’s model, and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. Expand
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